1. Field of the Invention
This invention relates to phase and frequency synchronized oscillatory circuits such as a phase lock loop. More particularly, this invention relates to circuits that detect loss of phase and frequency synchronization of an output timing signal of a phase lock loop with its frequency reference signal and provide an alarm indicative of the loss of synchronization.
2. Description of Related Art
In present high frequency digital communication and telecommunications systems, the network terminals must provide timing signals that synchronize with the incoming transport signals to recover the information. An exemplary telecommunication system is the Synchronous Optical Network (SONET). SONET is a standard for optical transport formulated by the Exchange Carriers Standards Association (ECS) for the American National Standards Institute (ANSI). ANSI generally set the standards for telecommunication within the United States.
SONET as the name implies is a synchronous network thus requiring all terminals on a SONET network to have internal clocking that is traceable to a highly stable reference clocking supply. The reference timing of a network terminal is embedded in the transport signal and the receiver synchronizes its local oscillator to the incoming embedded reference timing signal. Alternately, each terminal maybe connected to a building integrated timing supply (BITS). BITS is a highly accurate oscillator signal transferred independently of the transport signal for each terminal to achieve synchronicity.
Each terminal has a receiver to receive and buffer the transport signal. The receiver is connected to a clock extraction circuit that extracts the reference timing signal from the transport signal. The clock extraction circuit is connected to a phase lock loop that generates the local timing signal for the terminal. Alternately, the phase lock loop is connected to a BITS clock extractor, which extracts the highly accurate reference timing signal from the BITS communication link.
Clock extraction from the transport signal is well known in the art as illustrated in U.S. Pat. No. 5,963,608 (Casper et al.). Casper et al. has a data rate estimator that derives an estimate of the data rate of data contained in the digital data signal. A frequency estimator derives an estimate of the frequency of the output of phase lock loop. During an initial frequency acquisition mode, the sweep controller sequentially varies an analog voltage applied to the voltage controlled oscillator of the phase lock loop, until the estimate of the data rate effectively corresponds to the estimate of the frequency of the output of the voltage controlled oscillator. This terminates the frequency acquisition mode and initiates a phase acquisition mode. A loop filter is swept until the frequency of the phase lock loop equal to the actual frequency of the embedded clock signal, thereby locking the loop to the embedded clock.
The structure of a phase lock loop is well known in the art as shown in “Phase-Lock Loop-Based (PLL) Clock Driver: A Critical Look at Benefits Versus Costs,” Nayan Patel, SCAA033A, Texas Instruments, March 1997, and “Phase-Locked Loops for High-Frequency Receivers and Transmitters—Part 1” Curtin and O'Brien, Analog Dialogue, 33-3, 1999. Refer now to FIG. 1 for a brief review of the structure and operation of the phase lock loop. The key component of the phase lock loop 5 is a voltage controlled oscillator 25. The voltage controlled oscillator 25 may be crystal controlled oscillator (VCXO) or a surface acoustical wave (SAW) filter controlled oscillator (VCSO). The fundamental frequency of the voltage controlled oscillator as established by the crystal or SAW filter is adjusted or pulled in proportion to an input voltage signal VIN. Thus the frequency of the output timing signal Fout is modified in response to changes in the level of the input voltage signal VIN. The input reference signal Fref is the timing reference signal either embedded in the transport signal or provided by the BITS. The phase-frequency detector 10 receives the input reference signal Fref and a fedback form of the output timing signal Fout. The input reference signal Fref and the fedback form of the output timing signal Fout are compared to determine the phase and frequency equivalence of the input reference signal Fref and the fedback form of the output timing signal Fout. The phase-frequency detector 10 has an output UP indicating that the phase-frequency of the voltage control oscillator 25 needs to be adjusted to increase the frequency of the output timing signal Fout. The second output DOWN of the phase-frequency detector 10 indicated that the voltage controlled oscillator 25 needs to be adjusted to decrease the frequency of the output timing signal Fout. The output signal UP and DOWN of the phase-frequency detector 10 are the inputs to the charge pump 15. The charge pump 15 provides an output current ICP that is proportional to the desired frequency of the output timing signal Fout. The output current ICP is transferred to the low pass filter 20. The low pass filter 20 removes any undesired high frequency noise components that may be generated in the phase-frequency detector 15 or the charge pump 20 and creates the input adjustment voltage Vin for the voltage controlled oscillator 25.
As is known in the art the frequency of the input reference signal Fref may be a submultiple of the frequency of the output timing signal Fout. If this is the case for the design of the phase lock loop as illustrated, the frequency divider 30 is optionally placed in the feedback path of the output timing signal Fout. The frequency divider divides the frequency of the output timing signal Fout such that the input reference signal Fref is compared with a feedback signal that is a submultiple of the output timing signal Fout.
In digital phase lock loops the outputs UP and DOWN of the phase-frequency detector 10 are generally digital signals as shown in FIG. 2. In this example the phase frequency detector 10 determines phase and frequency synchronicity at the fall 30, 35, and 40 of the input reference signal. During the time period A, if the phase and frequency of the output timing signal Fout and input reference signal Fref are aligned, the signal UP and the signal DOWN have an equal pulse width. As shown during time period B, if the phase of the output timing signal Fout lags or the frequency is lower than the input reference signal Fref, the signal UP has a pulse width longer than the signal DOWN. If the phase of the output timing signal Fout leads or the frequency is higher than the input reference signal Fref, the signal DOWN has a pulse width longer than the signal UP. The charge pump 15 responds appropriately to create the necessary current ICP, which, when filtered, creates the input voltage VIN to adjust the voltage controlled oscillator 25.
Determination of phase-frequency lock of the phase lock loop 5 is important for the functioning of circuits that are to receive and extract the data from the transport signal. Generally, the circuits provide lock notification signals indicating that the phase lock loop is in phase-frequency synchronization. U.S. Pat. No. 6,215,834 (McCollough), U.S. Pat. No. 5,886,582 (Stansell), U.S. Pat. No. 5,870,002 (Ghaderi et al.), U.S. Pat. No. 5,838,749 (Casper et al.), U.S. Pat. No. 5,822,387 (Mar), U.S. Pat. No. 5,724,007 (Mar), and U.S. Pat. No. 5,394,444 (Silvey et al.) are illustrative of circuits and systems that provide such notification of the phase-frequency synchronization. These notification signals provide only an indication of phase-frequency synchronization and do not indicate a loss of phase-frequency synchronization. However, U.S. Pat. No. 4,499,434 (Thompson) does provide an alarm indicating loss of the phase-frequency synchronization.